---
title: "Building a World Model: Gemini Omni and the New TPU 8 Silicon"
description: "Google's 2026 silicon split shifts training and inference to TPU 8t and 8i, featuring the flattened Boardfly topology to enable continuous serving of massive agent swarms."
canonical: "https://zainahmed.net/blog/building-world-model-gemini-omni-tpu-8-silicon"
published: "2026-05-23"
---

# Building a World Model: Gemini Omni and the New TPU 8 Silicon

> Author: Zain Ahmed
> Published: 2026-05-23
> Read Time: 4 min read
> Category: Cloud Architecture
> Tags: TPU 8, Gemini Omni, Boardfly Topology, Silicon, Google Cloud
> Canonical URL: https://zainahmed.net/blog/building-world-model-gemini-omni-tpu-8-silicon

## Excerpt
Google's 2026 silicon split shifts training and inference to TPU 8t and 8i, featuring the flattened Boardfly topology to enable continuous serving of massive agent swarms.

---

The 2026 ecosystem pushes far beyond standard text generation and steps into physical simulation. Gemini Omni Flash processes audio, video, image, and text natively at the token level. It does this without relying on cascaded translation layers or bolted-on diffusion models.

This native processing allows Omni to function as a rudimentary world model. It intuitively calculates depth mapping, momentum, and fluid dynamic dispersion directly from 2D reference images and simple text instructions.

Google integrated the SynthID protocol directly into the model's logits processor to secure these outputs. SynthID does not alter pixels after generation. Instead, it uses a deterministic pseudorandom $g$-function to subtly augment the language model's natural probability scores. This embeds a cryptographic watermark that survives extreme compression and aggressive cropping.

<div className="max-w-sm mx-auto my-10">
  <img src="/assets/images/articles/google-rack-1999.webp" alt="Google's first production server rack, 1999" className="rounded-none border border-border/50 shadow-none w-full h-auto mb-3" />
  <p className="text-sm text-center text-muted-foreground">
    Google's first production server rack, 1999, hand-built by Larry Page and Sergey Brin, now on display at the Computer History Museum, Mountain View. The foundation Google's silicon empire was built on.<br/>
    <span className="italic">Source: Google Cloud (cloud.google.com)</span>
  </p>
</div>

## The Silicon Split: TPU 8t vs. TPU 8i

Training a world model and serving a fast agentic loop require very different hardware. The demands are now mutually exclusive. Because of this, Google officially split its silicon roadmap into two distinct paths.

<div className="grid gap-6 md:grid-cols-2 my-8 not-prose">
  <card className="border-blue-500/20 bg-blue-500/5 ring-1 ring-blue-500/5">
    <cardheader>
      <svg xmlns="http://www.w3.org/2000/svg" width="20" height="20" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round" className="text-blue-500"><path d="M21 16V8a2 2 0 0 0-1-1.73l-7-4a2 2 0 0 0-2 0l-7 4A2 2 0 0 0 3 8v8a2 2 0 0 0 1 1.73l7 4a2 2 0 0 0 2 0l7-4A2 2 0 0 0 21 16z"/></svg>
      <cardtitle className="text-blue-600 dark:text-blue-400 font-bold">TPU 8t (Training)</cardtitle>
    </cardheader>
    <cardcontent>
      Engineered for massive-scale pre-training, the TPU 8t operates in a 3D torus topology. A single superpod holds 9,600 chips. The Virgo Network unifies the entire setup. This non-blocking fabric links up to 134,000 chips with 47 petabits per second of bi-sectional bandwidth. It also utilizes native FP4 support to double the throughput of the Matrix Multiply Unit.
    </cardcontent>
  </card>

  <card className="border-purple-500/20 bg-purple-500/5 ring-1 ring-purple-500/5">
    <cardheader>
      <svg xmlns="http://www.w3.org/2000/svg" width="20" height="20" viewBox="0 0 24 24" fill="none" stroke="currentColor" stroke-width="2" stroke-linecap="round" stroke-linejoin="round" className="text-purple-500"><path d="M9.5 2A2.5 2.5 0 0 1 12 4.5v15a2.5 2.5 0 0 1-4.96.44 2.5 2.5 0 0 1 0-3.88 2.5 2.5 0 0 1 0-3.88 2.5 2.5 0 0 1 0-3.88A2.5 2.5 0 0 1 9.5 2Z"/><path d="M14.5 2A2.5 2.5 0 0 0 12 4.5v15a2.5 2.5 0 0 0 4.96.44 2.5 2.5 0 0 0 0-3.88 2.5 2.5 0 0 0 0-3.88 2.5 2.5 0 0 0 0-3.88A2.5 2.5 0 0 0 14.5 2Z"/></svg>
      <cardtitle className="text-purple-600 dark:text-purple-400 font-bold">TPU 8i (Inference)</cardtitle>
    </cardheader>
    <cardcontent>
      The 8i was built specifically to break through the memory wall of high-concurrency reasoning. It features a massive 384 MB of on-chip SRAM, a 300% increase over the previous generation. This allows the entire active Key-Value cache to live directly on the silicon, which completely eradicates data-fetching lag.
    </cardcontent>
  </card>
</div>

To speed up Mixture-of-Experts routing, the 8i ditches the 3D torus in favor of the Boardfly topology.

### Understanding the Hops reduction

In a standard 1,024-chip 3D torus, the worst-case packet traversal is 16 hops.

<div className="my-6 p-6 rounded-none border border-border/50 bg-[#0d1117]/50 font-mono text-center overflow-x-auto text-foreground">
  3D torus hops = (8/2)X + (8/2)Y + (16/2)Z = 16 hops
</div>

The flattened Boardfly topology reduces this maximum path to just **7 hops**. Google combined this with a dedicated Collectives Acceleration Engine to cut on-chip communication lag by up to a factor of five. This delivers an 80% performance-per-dollar improvement. It finally makes the continuous serving of massive agent swarms economically viable.

---

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